Commutation Failure Elimination of LCC HVDC Systems Using Thyristor-Based Controllable Capacitors

The adverse impacts of commutation failure (CF) of a line-commutated converter (LCC)-based high-voltage direct current (HVdc) system on the connected ac system are becoming more serious for high-power ratings, for example, the development of ultra-HVdc systems. Aiming to solve the problem of CF particularly for higher power/current LCC HVdc systems, this paper proposes a new method, which utilizes a thyristor-based controllable capacitor (TBCC), to eliminate CFs. The topology of the proposed TBCC LCC HVdc and its operating principles are presented. Then, mathematical analysis is carried out for the selection of component parameters. To validate the performance of the proposed method, modified LCC-HVdc and capacitor-commutated converter (CCC)-based HVdc systems based on the modified CIGRE HVdc system are modeled in a real-time digital simulator. Simulation studies for zero impedance single-phase and three-phase faults are carried out, and comparisons are made with both LCC-HVdc and CCC-HVdc systems. Furthermore, voltage and current stress of the TBCC are investigated and power-loss calculations are presented. The results show that the proposed method is able to achieve CF elimination under the most serious faults while the increase of power losses due to the TBCC is small.

been completed or under construction [5], and the rated transmission power of these projects are between 5 GW to 12 GW. This increased level of power transmission means that the scale of the impact of Commutation Failure (CF) on the AC system is increased. For cases when CF does not cause converter blocking, there will be a more significant reduction of inverter AC system frequency and a higher power shift to the adjacent HVAC lines. For cases when CF causes the blocking of converter stations, the potential economic loss due to the loss of active power transfer is certainly higher. For example, significant generator tripping at rectifier side and the activation of spinning reserves at inverter side are required to compensate the loss of active power transfer. In extreme cases, this cessation of active power transfer can even lead to the blackout of inverter side AC system. Therefore it would be useful to develop new approach to eliminate CF for the latest generation of higher power rating LCC HVDC (e.g., UHVDC).
A number of publications have been dedicated to the mitigation of CF. As discussed in [6], they can be classified into 1) controller modification based methods [7]- [13], and 2) power electronics based methods [14]- [20].
Most of the controller modification based methods are aiming to mitigate successive CFs rather than eliminate CFs. They rely on fast and accurate detection of inverter side faults and are designed to provide a larger commutation margin by advancing inverter firing angles. The main differences between these methods are 1) the way of fault detection, and 2) the way of calculating the firing angle advancement. Reference [8] uses the abc − αβ transformation for detection of single-phase and three-phase faults, and reference [12] uses a power component fault detection method to improve the detection of single-and three-phase faults. For the calculation of firing angle advancement, [10] and [13] uses fuzzy logic based controllers to determine the extent of firing angle advancement. Reference [7], [9], [11], on the other hand, directly use the inverter AC voltage to calculate the desired firing angle. Improvements in mitigating successive CF can be achieved with these methods but it should be noted that by decreasing the inverter firing angle, inverter reactive power consumption is increased, which leads to further AC voltage drops. Such behavior is unfavorable as a higher AC voltage is needed for a better recovery. Furthermore, as pointed out by [21], CF cannot be eliminated by pure controller modifications.
The most well known main equipment based method in CF mitigation is the Capacitor Commutated Converter (CCC) based This work is licensed under a Creative Commons Attribution 3.0 License. For more information, see http://creativecommons.org/licenses/by/3.0/ HVDC [15]. With fixed series capacitor insertions, it can reduce the CF probability but additional valve voltage stress is reported. Also it experiences slower recovery from unbalanced fault [22]. To improve the controllability of inserted capacitors, active series compensations with the help of Insulated Gate Bipolar Transistor (IGBT) are adopted in [6], [17]. However due to the limited current handling capability of IGBTs compared with thyristors, their application in LCC HVDC systems with higher power/current ratings (e.g., UHVDC systems) is limited. Recently an Evolved Capacitor-Commutated-Converter (ECCC) embedded with Anti-Parallel Thyristors based Dual-directional Full-Bridge Module (APT-DFBM) was proposed in [23] to mitigate CF and to improve the dynamic performance of CCC HVDC. The use of thyristors avoids the limitation of current rating from IGBTs and the probability of CF is reduced. A comparison between the proposed method in this paper and the method of ECCC is provided in Section VII. Reference [24], from a different prospective, uses a superconducting fault current limiter to achieve faster recovery by limiting the AC fault current. Another family of power electronics based methods uses shunt connected reactive power compensation devices at the inverter AC side [25], [26]. Those devices are utilized to help the recovery of AC voltage especially during remote fault so that the risk of CF can be reduced. However, they cannot eliminate CFs and the cost of equipment can be significant considering their application in UHVDC projects.
To eliminate CF especially for LCC HVDC systems with higher power/current ratings (e.g., UHVDC systems), this paper proposes an approach using Thyrsitor Based Controllable Capacitor (TBCC). The use of thyristors effectively alleviates the limitation introduced by the present handling capability of IGBTs, and therefore makes it applicable to UHVDC systems. In addition, due to lower power losses of thyristors, the use of TBCC has the extra benefits of lower extra power losses than that using IGBTs. This paper is organized as follows. In Section II, circuit configuration of TBCC is described. In Section III, the operating principles of TBCC and capacitor voltage control are explained. In Section IV, detailed mathematical analysis is carried out for the selection of component parameters in TBCC. In Section V, simulation results of the proposed system under single-and three-phase faults are presented to validate the effectiveness of the proposed method. Comparisons are made between the proposed TBCC LCC HVDC, LCC-HVDC and CCC-HVDC. In addition, voltage and current stresses of TBCC are investigated. In Section VI, calculations of additional power losses introduced by TBCC are carried out. Finally conclusions are drawn in Section VII.

II. CONFIGURATION OF THE THYRISTOR BASED
CONTROLLABLE CAPACITOR Fig. 1 shows the proposed converter configuration at inverter side of the HVDC system. In Fig. 1(a), one 6-pulse thyristor bridge of the 12-pulse inverter is shown where I d is the DC current, L s is the DC smoothing reactor, T Y 1 − T Y 6 are thyristor valves. The complete system is based on the CIGRE HVDC Benchmark model which is a 12-pulse system rated at 1000 MW, 500 kV and 2 kA [27]. Fig. 1(b) shows the circuit configuration of one TBCC module. In Fig. 1(b), C is the main capacitor, T 1 and T 2 are the main thyristors, and each of them is equipped with an anti-parallel diode, i.e., D1 and D2, respectively. There are two commutation circuits for turning off the two main thyristors. The first commutation circuit consists of an LC resonant branch, i.e., the branch with inductor L1a and capacitor C1a, and two auxiliary thyristors, T 3a and T 5a. The second commutation circuit has the same configuration as the first one with inductor L2a and capacitor C2a forming the resonant branch, and two auxiliary thyristors, T 4a and T 6a.
The positive direction of current I phase , the positive voltage polarities of the main capacitor V cap and two auxillary capacitors C1a and C2a are also shown in the figure. Each TBCC module can be implemented by a single module or by a number of series connected sub-modules for higher voltage insertions. It should be mentioned that as there is no IGBT, the power handling capability of the TBCC is significantly increased compared with IGBT based modules.
There are two modes of operation for TBCC, i.e., capacitor insertion mode and capacitor bypass mode. For positive I d , the main capacitor is bypassed or inserted when the current is flowing through T 1 or through D2, respectively. For negative I d , the main capacitor is bypassed or inserted when the current is flowing through D1 or through T 2, respectively. For both current directions, the positive polarity of the main capacitor is connected to the DC side when inserted. The detailed insertion strategy of TBCC is explained in the next section.

III. OPERATING PRINCIPLE AND CAPACITOR VOLTAGE CONTROL
The TBCC in phase C is considered in this section. The steps for initial charging and the detailed operating principles are explained first, and then the method of controlling the capacitor voltage is presented.

A. Initial Charging of TBCC Module
There are five steps for the initial charging of TBCC module. Fig. 2 shows the active conduction path for each step, and the details of each step are described as follows: Step 1: The main capacitor is charged with positive I phase ; Step 2: T 2 and T 3a are fired and C1a is charged by the main capacitor to the polarity shown in Fig. 2. When the voltage across C1a is equal to the main capacitor, the  charging is completed and T 2 and T 3a are turned off; Step 3: T 5a is fired, forming a resonant circuit between C1a, L1a and T 5a. Once resonance is completed, the voltage polarity of C1a is reversed; Step 4: Similar to step 2, C2a is charged to the polarity shown in Fig. 2 by firing T 1 and T 4a; Step 5: Similar to Step 3, T 6a is fired to form a resonant circuit between C2a, L2a and T 6a. The voltage polarity of C2a is reversed once the resonance is completed. The voltage of the main capacitor during operation is controlled by the voltage controller described in subsection C of this section. The voltages of C1a and C2a during operation depend on the circuit parameters and the voltage of the main capacitor. Detailed analysis is provided in Section IV.
To explain the operating principles of TBCC, Fig. 3 is used to show the control sequence of TBCC throughout one cycle. Fig. 3(a) shows the phase C current, key timing instants (t 1 -t 13 ) and key firing instants of thyristors. The positive direction of phase C current is defined as flowing out of the converter to the AC system. Fig. 3(b) illustrates the change of main capacitor voltage within the same cycle. The active conduction paths under different stages are shown and highlighted in Fig. 4.

B. Operating Principle
With the voltages of C1a, C2a and C initially charged to the polarity shown in Fig. 1(b), the detailed operating principle can be described as follows with reference to Figs. 3 and 4.
Stage 1 (t 1 -t 2 ): T 2 is fired as commutation starts from T Y 3 to T Y 5 at time t 1 . The phase current is flowing through T 2 and the main capacitor C to the DC side, discharging the main capacitor as shown in Fig. 3(b). Due to the insertion orientation, the main capacitor is providing extra commutation voltage; Stage 2 (t 2 -t 3 ): T 4a is fired once the commutation from T Y 3 to T Y 5 is completed. A resonant circuit is formed between C2a, L2a, T 4a and T 2, and the resonant current through T 2 is in the opposite direction of the phase current. The voltage of C2a is added across L2a and the resonant current is flowing within the resonant loop, resulting in negligible impact on the harmonic performance of LCC HVDC. T 2 is turned off when the resonant current is higher than the phase current, and T 4a is turned off once the resonant current reaches zero at t 3 . At the end of this stage, voltage polarity of C2a is reversed and the main capacitor voltage is further reduced; Stage 3 (t 3 -t 6 ): with T 2 and T 4a turned off, phase C current flows through D1 into the converter; Stage 4 (t 4 ): T 6a is fired at t 4 , forming another resonant circuit between C2a, L2a and T 6a. Once resonance is completed, the C2a voltage polarity becomes positive again preparing for the turn-off action in next cycle; Stage 5 (t 7 -t 9 ): T 1 is fired as commutation starts from T Y 6 to T Y 2 at time t 7 . The phase current flows through T 1 to the AC side, and the main capacitor is bypassed; Stage 6 (t 9 -t 10 ): T 3a is fired at t 9 , forming a resonant circuit between C1a, L1a, T 3a and T 1. T 1 is turned off when the resonant current is higher than the phase current, and T 3a is turned off once resonant current reaches zero at t 10 . At the end of this stage, voltage polarity of C1a is reversed; Stage 7 (t 10 -t 12 ): with T 1 and T 3a turned off, phase current flows through the main capacitor and D2 to the AC side, charging the main capacitor. This insertion orientation helps the commutation from T Y 2 to T Y 4 between t 11 to t 12 . It needs to be mentioned that the charging time of the main capacitor (t 10 -t 12 ) is longer than the discharging time (t 1 -t 3 ). This is because the average discharging current (between t 1 -t 2 ) is higher than the charging current (t 11 -t 12 ) during commutations ( Fig. 3(a)). Therefore additional charging time is required to control the capacitor voltages; Stage 8 (t 13 ): T 5a is fired at t 13 , forming a resonant circuit between C1a, L1a and T 5a. Similar to stage 4, the voltage polarity of C1a becomes positive again after resonance preparing for the turn-off action in next cycle.
It can be seen from the above description for TBCC in phase C, additional commutation voltages are obtained for two com-  mutation periods, i.e., from T Y 3 to T Y 5 and from T Y 2 to T Y 4. Similar operating principles are applied to the TBCCs in other two phases, and as a result all six commutation periods are helped by the insertion of TBCCs. With sufficient insertion voltage, the success of commutations can be ensured.

C. Capacitor Voltage Control
The level of main capacitor voltage needs to be controlled to ensure the success of commutations. To illustrate the control strategy, the same TBCC in phase C is taken as an example. Fig. 5 shows the phase C current and the commutation voltage of e ca , and Fig. 6 shows the capacitor voltage controller for TBCC in phase C. From Fig. 3(b) it can be seen that the main capacitor is discharged during the commutation from T Y 3 to T Y 5, and is charged from the turning-off point of T 3a until the end of commutation from T Y 2 to T Y 4. Therefore the level of main capacitor voltage can be controlled by controlling the firing instant of T 3a. The firing instant (t 9 ) should be later than t 8 , and the turning-off of T 3a (t 10 ) should be earlier than t 11 so that full DC current is utilized for charging. The actual firing instant for T 3a is obtained through a PI controller by minimizing the capacitor voltage error as shown in Fig. 6. In the figure, V ref and V meas T B C C −C are the reference and measured capacitor voltages, T B C C −C are the minimum, maximum and actual firing angles for T 3a. To calculate the T 3a firing angle limits, Fig. 5 is used for the following calculations. With the positive zero-crossing point of e ca as the phase reference, α is the firing angle for T Y 4 and γ is the extinction angle. Then the firing angle limits for T 3a can be calculated as where ω is the system angular frequency and T osc is the resonant period of C1a and L1a, which can be calculated as where L 1 and C 1 are the inductance and capacitance of L1a and C1a, respectively. If the measured main capacitor voltage is lower than the reference, the firing angle for T 3a will be advanced to charge up the voltage, otherwise it is delayed to provide less charging. In this way the main capacitor voltage can be controlled at its reference level to provide sufficient commutation voltage. The balancing of voltages between sub-modules is achieved by applying the controller shown in Fig. 6 to each sub-module. In this way the balancing of capacitor voltages are automatically achieved, and no additional control coordination is required. The same control strategy is applied to TBCC in other phases except the use of different phase references.

IV. THEORETICAL ANALYSIS AND PARAMETER SELECTIONS
For satisfactory operation of TBCC, the following component parameters need to be determined: 1) capacitance and inductance of the commutation circuits, i.e., C 1 , C 2 , L 1 and L 2 ; 2) capacitance and voltage reference of the main capacitor. In this section, detailed mathematical analysis is carried out, and based on that component parameters are selected.

A. Dynamics of the Commutation Circuits
As the behavior of commutation circuits are the same, only one is considered here. Fig. 7 shows the electrical variables associated with the commutation circuit for T 2 of TBCC in phase C. In Fig. 7, t 0 is the start of commutation from T Y 3 to T Y 5, t A is the end of commutation, t B is the time instant when D2 is turned off, t C is the time instant when T 4a is turned off, i LC is the resonant current, I max is the maximum resonant current and V 0 is the voltage of C2a before t A .
The behavior of commutation circuit can be divided into two periods. Period 1 (t A -t B ) is the period between the firing of T 4a and the turning-off of D2. Period 2 (t B -t C ) is the period between the turning-off of D2 and the turning-off of T 4a. The equivalent circuits for both periods are shown in Fig. 8. According to Fig. 8(a), the dynamic equations for period 1 can be where I d is the DC current, v c is the voltage of C2a, R T 4a is the resistance of T 4a and R D 2 is the resistance of D2. As T 2 is turned off shortly after the firing of T 4a, its resistance is not considered. Solve (4)-(5) with the initial conditions of (6)- (7) and take t A as the time reference, C2a voltage is obtained as v c (t) = K 1 e − a 2 t cos ω n t + K 2 e − a 2 t sin ω n t − I d R D 2 (8) where Substitute (8) into (5), the resonant current is obtained as As the resonant period is short and the loop resistances are small, the resonant current can be approximated by For period 2, with reference to Fig. 8(b), the dynamic equations and the associated initial conditions are where the superscripts denote the variables for period 2. The value of V cap is considered to be constant in period 2 as the main capacitance is much larger than the auxiliary capacitance. As period 2 is very short, resistances in the circuit are neglected.
Considering (16)- (17) and take t B as time reference, C2a s voltage and resonant current can be calculated: v c (t) = K 1 cos ω n t + K 2 sin ω n t + V cap (19) i LC (t) = −C 2 K 1 ω n sin ω n t + I d cos ω n t where Considering the resonant current becomes zero at t C , the C2a voltage at t C can be calculated as It can be seen from (24) that the voltage of C2a is dependent on the main capacitor voltage at t C . The phase current I phase is charging C2a between t B and t C to compensate for the losses of resonant circuit. Therefore the voltage of C2a will not decrease due to the losses in the resonant circuit as long as the main capacitor voltage is controlled.

B. Parameter Selection for Main Capacitor
The capacitance value for the main capacitor is chosen so that the variation of its voltage is not significant after each discharge/charge period. According to the analysis carried out in [6], considering the increase of DC current, the value of 880 μF is chosen for simulation study. For the required voltage level of the main capacitor, a value of more than 200 kV should be required [6]. However in the proposed method as the capacitor modules are taking part in the formation of DC voltage, and an early insertion before the start of commutation reduces the increase of DC fault current, the required voltage insertion is less. The value of the main capacitor voltage reference is obtained as 200 kV from simulation studies.

C. Parameter Selection for Commutation Circuits
Two requirements are considered for the selection of commutation circuit parameters. The first requirement is that the maximum resonant current I max should be higher than the maximum DC fault current. In this paper, I max of 10 kA is chosen as an example. It should be noted that modern thyristors have no problem handling such level of current given the short resonant period. The average and RMS value of resonant current are well within the allowable range of thyristors which are demonstrated in Section VI. The second requirement is that the available charging time of the main capacitor should be sufficiently longer than the discharging time. With reference to Figs. 3(a) and 5, the available discharging and charging time of the main capacitor outside commutation period are given as where μ is the overlap angle. The second requirement can then be expressed as where k is the margin factor and is chosen as 1.3 for sufficient charging time. Simplify (27) by substituting (25) and (26) gives To find the required range of L 2 and C 2 , additional relationship between them is required. This can be obtained by analyzing the energy loss and voltage drop of C2a within one cycle. The main energy loss of commutation circuit for T 2 is coming from the resonant circuit as shown in Fig. 8 between t A and t B , and a minor part from the resonant circuit of T 6a − L2a − C2a after the firing of T 6a.
The total energy loss in one AC cycle can be calculated as where R T 6a is the resistance of T 6a. Define ΔV as the associated voltage drop of C2a, E loss can also be expressed as where Under steady-state, the losses should be compensated by the charging action between t B and t C , i.e., v c (t C ) = V 0 + ΔV Now by substituting (31) and (33) into (24), the equation for solving V 0 can be obtained as With the specified I max , V 0 can be calculated using (34), and the relationship between L 2 and C 2 is obtained by considering The ranges of values for L 2 and C 2 can be calculated by solving (35) and (28) together: The overlap angle of 15 degrees, equivalent resistances of 0.1 ohm and the m of 0.6 are used for the above calculation. As an example, 40 kV of V cap is chosen which indicates five such modules are needed to provide the 200 kV insertion.

A. Fault Dynamics of 500 kV/3 kA HVDC System
To validate the effectiveness of the proposed method, simulation results for zero impedance single-phase and three-phase faults are presented, and comparisons are made with LCC-HVDC and CCC-HVDC. All three systems are established based on the CIGRE benchmark model with their rated DC current increased to 3 kA. The sizes of capacitor banks for the LCC-HVDC and the proposed system are increased to accommodate the increase of reactive power consumption. For CCC-HVDC, the capacitor banks and filters are providing 15% of the reactive power [16]. The series capacitance of 90 μF is selected for CCC-HVDC so that the average commutation voltage being provided during commutation is similar to that of the proposed method. The inductances of 0.005 H and capacitances of 130 μF are chosen for all commutation circuits. Fig. 9 shows the simulation results of 60 ms zero impedance phase C to ground fault at inverter side. When fault is initiated at 0.08 s, phase C voltage drops to zero as shown in Fig. 9(a). It can be seen from Fig. 9(c) that there is no CF in the proposed system, while CF can be observed in both CCC-HVDC and LCC-HVDC systems from Fig. 9(d) and (e). As a result, the DC voltage of the proposed system does not drop to zero ( Fig. 9(b)), enabling the system to transmit active power during the fault period ( Fig. 9(f)). On the other hand, the DC voltages drop to zero for CCC and LCC as shown in Fig. 9(b) and hence no active power can be transmitted ( Fig. 9(f)). Fig. 9(g) shows that the insertion voltages from TBCC are well controlled. Fig. 10 shows the simulation results of 110 ms zero impedance three-phase fault at inverter side. When fault is initiated at 0.13 s, three-phase voltages drop to zero as shown in Fig. 10(a). However, as illustrated in Fig. 10(c), no CF occurs in the proposed method. For CCC-HVDC shown in Fig. 10(d), first few commutations are successful due to additional commutation voltage from fixed capacitors but CFs can be observed when capacitor voltage drops. For LCC-HVDC, CF occurs once the fault is triggered (Fig. 10(e)). DC voltage and active power drop to zero in all three systems but the proposed system achieves a faster recovery as shown in Fig. 10(b) and (f). Also from Fig. 10(b) and (f), it can be seen that CCC-HVDC recovers faster than LCC-HVDC. This is due to the less reactive power absorption of CCC-HVDC during recovery. Again the insertion voltage is well controlled during fault as shown in Fig. 10(g). Fig. 10(h) shows the zoomed-in plot of capacitor voltages between 0.25 s and 0.3 s. The same key timing instants for phase C as those shown in Fig. 3(b) are included. It can be seen that the phase C capacitor voltage is decreased for commutation from T Y 3 to T Y 5 (t 1 − t 2 ), and is further decreased until the capacitor is bypassed (t 3 ). As the capacitor voltage is lower than the reference (because of the fault), it is inserted into the circuit at t 10 to charge up the voltage until commutation from T Y 2 to T Y 4 is completed (t 12 ).

B. Fault Dynamics With Larger AC Systems
To demonstrate the capability of the proposed method with larger AC systems, the system as shown in Fig. 11 is    established in RTDS where the IEEE 39-Bus system [28] is used to represent the AC systems of both rectifier and inverter sides. The synchronous generators, excitation systems and governor systems are modelled in detail. The rectifier side is connected to bus 36 and the inverter side is connected to bus 26 (the full single-line diagram is not shown here due to the page limit and the same bus numbers as those in [28] are used). Fig. 12 shows the simulation results of the system under 60 ms zero impedance single-phase fault at inverter AC bus. It can be seen from Fig. 12(a) that CF does not occur and the HVDC system is able to transmit active power during fault ( Fig. 12(b)). Fig. 12(c) shows the rotor speeds of the synchronous generators (G6 and G7) that are electrically close to bus 36 and Fig. 12(d) shows the rotor speeds of the synchronous generators (G8 and G9) that are electrically close to bus 26 (the same numbering system for generator as those in [28] are used). It can be seen that the rotor speeds at rectifier side are increased due to the drop of active power transfer. The inverter side rotor speeds are increased as fault happens due to the drop of bus voltages and are then decreased due to the decrease of active power from HVDC.

C. Fault Dynamics of 800 kV/4 kA UHVDC System
To further demonstrate the capability of the proposed method, a UHVDC system rated at 800kV/4kA is established based on the CIGRE benchmark system. Due to the increased rating of UHVDC system, the required insertion voltage level from TBCC is increased, and the value of 250 kV is obtained from simulation studies. Figs. 13-15 show the simulation results of the system under single-phase fault (phase C to ground), three-phase fault and double-phase to ground fault (phase A and  phase B to ground), respectively. For single-phase fault, it can be seen from Fig. 13(a) that phase C voltage (green) is dropped to zero during the fault, but no CF is observed as shown in Fig. 13(c). As a result, the UHVDC system is able to maintain a non-zero DC voltage (Fig. 13(d)) and transmit active power during the fault (Fig. 13(b)). For three-phase fault, the threephase voltages are dropped zero as shown in Fig. 14(a), but no CF occurs due to the insertion of TBCC modules (Fig. 14(c)). Similar to Fig. 10, the DC voltage drops to zero (Fig. 14(d)) and there is no active power transfer during the fault (Fig. 14(b)). For double-phase to ground fault, the phase A and phase B voltages are dropped to zero as illustrated in Fig. 15(a). As shown in Fig. 15(c), no CF occurs during the fault period. The DC voltage drops to zero after fault is initiated and then recovers due to the controller actions (Fig. 15(d)). A certain level of active power can be transmitted during the fault as shown in Fig. 15(b).

D. TBCC Performance
To better illustrate the performance of TBCC in detail, Fig. 16 shows the detailed waveforms within TBCC of phase C. The same time instants as those shown in Figs. 3 and 7 are used, and the capacitor reference voltage of 40 kV is considered. The currents flowing through IT Y 2 and IT Y 5 are shown in both Fig. 16(a) and (b) for time references. The firing sequences and the change of main capacitor voltage shown in Fig. 16(a) are the same as those described in Section III and are not repeated here. It can be seen from Fig. 16(a) that the peak resonant current for turning off T 1 and T 2 is about 10 kA, hence both T 1 and T 2 are turned off shortly after the firing of T 4a and T 3a. The bottom plot of Fig. 16(a) shows the current through the main capacitor. It is the same as the current through T Y 5 after T 2 is fired at t 1 , and the current through T Y 2 when T 3a is turned off at t 10 . It should also be mentioned that the firing of T 5a before the turning off of T Y 2 is due to the early firing of T 3a. Fig. 16(b) shows the voltages of T 1 − T 2, T 3a − T 6a, and C1a and C2a. From Fig. 16(b), it can be seen that once T 4a is fired at t 2 , the voltages across T 4a and T 6a drops to zero. The voltage of C2a starts to decrease due to resonance. At time t B , when the oscillation current is equal to the DC current, T 2 and D2 are turned off so T 2a voltage is equal to the main capacitor voltage, and the voltage of C1a is added across T 3a. Next when T 4a is turned off at t C , its voltage is equal to the voltage difference between C2a and the main capacitor. At the same time T 6a is experiencing the voltage of the main capacitor. The voltage of C2a is kept unchanged as resonance is completed. At t 4 , T 6a is fired and starts to conduct, so T 6a voltage drops to zero and T 4a is experiencing the main capacitor voltage. The voltage of C2a starts to reverse as resonance continues. At the time instant when T 6a is turned off as highlighted in Fig. 16(b), C2a voltage is reversed and is added across T 6a. The voltage of T 4a is equal to the sum of main capacitor voltage and C2a voltage. T 3a is experiencing the voltage of C1a as T 1 is conducting. At t 6 when commutation from T Y 5 to T Y 1 is completed, T 2 voltage drops and is increased again to the main capacitor voltage when T 1 is fired at t 7 . The voltage of T 1 is the difference of the main capacitor voltage and the voltage across T 2. At t 9 when T 3a is fired, its voltage and the voltage of T 5a drop to zero. The voltage of C1a starts to reverse because of resonance. When T 1 and D1 are turned off shortly before t 10 , C2a voltage is added across T 4a, and T 2 voltage drops to zero. The change of voltage across T 5a is the same as the voltage across T 6a in the first half cycle and is not repeated here. When T 5a is fired at t 13 , the voltage of C1a starts to  reverse due to resonance. From the above analysis it can be seen that the highest valve voltage appears on T 4a, and is equal to the sum of main capacitor voltage and C2a voltage. A series connection of multiple thyristors can be utilized to make sure the forward voltage across each thyristor is within allowable range. It can also be seen that the voltage imposed on TBCC module is mainly determined by the voltage level of the main capacitor. Therefore under fault conditions, the voltage imposed on the TBCC will be decreased with decreased main capacitor voltage (Figs. 9(g) and 10(g)).
In terms of harmonic impact from TBCC, Table I shows the comparisons of THDs for AC voltage and current between the benchmark system and the proposed method. It can be seen that the THDs are increased due to the capacitor insertions but are still within acceptable limits.

VI. ESTIMATION OF POWER LOSS
The increase of power losses due to additional TBCCs is estimated in this section. As an example, the Phase Controlled Thyristor (PCT) with a rated voltage of 7.2 kV and rated average on-state current of 4840 A [29], and the power diode of [30] are used for calculation. Using the same design as described before, 5 sub-modules are required for each phase and 30 sub-modules are required for the 12-pulse inverter.
To calculate the power losses from each sub-module, Table II shows the conduction period and the corresponding device of one sub-module from Phase C with reference to Figs. 2 and 3. By using the overlap angle of 15 • and Δt of 0.5 ms, the associated average and RMS currents are calculated and shown in the table (valve currents during commutations are assumed to be linear for simplicity). These values are then used to calculate the on-state power utilizing the equation [31]: where V 0 is the threshold voltage, r is the slope resistance, I av is the average current, and I rms is the RMS current. For the calculations of thyristor and diode, the corresponding threshold voltage and slope resistance are obtained from datasheet. The turn-on losses of thyristor and diode are neglected. Then by substituting the data into (38), the on-state power loss for each individual component is obtained. That is further scaled to get the loss for each module, and then finally the total extra power loss for the 12-pulse inverter, which is calculated to be 2.954 MW. Consider the 1500 MW rating of the HVDC system and that the TBCCs are only installed at inverter side, the percentage of loss increase per converter station is calculated as 2.954/1500/2 = 0.0985%. It will increase the capitalized cost of converter station. However the economic savings of CF elimination are significant and can potentially justify the increased cost. Firstly the proposed method improves the availability of the UHVDC system, as the system may not need to be blocked and is able to ride through the inverter AC faults. The resulting additional electrical energy that can be transmitted with the proposed method is significant and directly results in cost savings. Secondly due to the ability of transmitting active power during faults, the economic savings can be achieved from 1) the reduction of the level of load shedding and activation of spinning reserve at inverter side and 2) the reduction of the level of generation tripping at rectifier side. Consider the high power rating of UHVDC and the restoration time of the tripped generators (up to hours), the potential savings are significant. Thirdly, the risks of system instability and blackout due to CF are reduced with the proposed method. As the number and rating of UHVDC systems continue to increase, the risks of AC system instability and blackout are increased. Consider the potentially huge economic loss from these risks, the savings can be significant.

VII. DISCUSSION AND COMPARISON
In this section, a comprehensive comparison is made between the proposed method and the method from [23]. The aspects of 1) system performance; 2) component usage & cost; 3) efficiency and 4) control complexity are considered. In terms of system performance, the proposed method is able to achieve the elimination of CF while the method in [23] is to mitigate CF. It is due to the difference of controllability between TBCC module and the APT-DFBM. The TBCC module has full controllability of its capacitor voltage during operation, and hence can control the additional commutation voltage being provided. The commutation voltage provided by APT-DFBM cannot be actively controlled and is mainly determined by the DC current and the pre-determined size of the capacitor. Therefore it is difficult for APT-DFBM to provide a larger voltage-time area for successful commutations during serious faults with a very large AC voltage drops.
To facilitate the comparison of component usage & cost, the same single-phase fault as described in [23] has been simulated using the proposed method. The required voltage level from TBCC to achieve CF elimination is 33 kV and the operating voltages of C1a and C2a are 40 kV. According to the analysis in Section V, the maximum voltages experienced by T 1/T 2, T 3a/T 4a and T 5a/T 6a are 33 kV, 73 kV and 40 kV, respectively. Consider the same acceptable steady-state voltage of 4 kV for each thyristor, the numbers of thyristors for T 1/T 2, T 3a/T 4a and T 5a/T 6a are 9, 19 and 10, respectively. Therefore the total number of thyristors in the TBCC module is 9 × 2 + 19 × 2 + 10 × 2 = 76. Further considering the capacitors and inductors from commutation circuit, the number of component used and the associated cost for the TBCC module is higher than that of the APT-DFBM module (8 × 10 = 80 thyristors). It is understandable as better controllability is achieved with TBCC at the cost of additional components. To achieve complete elimination of CF under 100% voltage drop as proposed in this paper, more TBCC modules are required and results in higher investment cost. However, the practical implementation of the proposed method will always be a tradeoff between the investment cost and the potential economic savings. For example it may not always be necessary to design the TBCC for 100% voltage drop, given that CFs are mostly caused by remote faults with limited AC voltage drops.
For comparison of efficiency, the same TBCC module with 33 kV is used. Using the calculation method from Section VI but for the 500 kV/2kA system, the loss is calculated to be 0.432 MW. This is 0.0432% increase of power loss, which is lower than the 0.062% calculated in [23]. It is because only one thyristor element is in conduction during normal operation (T 1 or T 2) for the TBCC module, while there are two in the APT-DFBM.
In terms of control complexity, the required measurement signals for each TBCC module are the current through the module and the main capacitor voltage. For the APT-DFBM module, in addition to these two signals, additional signals for fault detection and fault clearance are required. Furthermore the TBCC only needs to control its main capacitor voltage during operation. The APT-DFBM module has several control modes during operation and coordination between them is required depending on the fault and capacitor voltage. Such coordination is not required for the TBCC modules.

VIII. CONCLUSION
The TBCC module has been proposed in this paper to achieve the elimination of CF for UHVDC systems. The module is based on thyristors only hence the proposed method is suitable for UHVDC systems with higher power/current ratings. Detailed operating principles, capacitor voltage control strategy and mathematical analysis of the TBCC module have been explained, and the selection of parameters has been given. To validate the effectiveness of the proposed method, comparisons are made with CCC-HVDC and LCC-HVDC using systems rated at 500 k V/3 kA. Additional simulation results of the HVDC with larger AC systems (IEEE 39-bus system) at both rectifier and inverter sides have been presented. 800 kV/4 kA system is further developed and simulated to demonstrate the capability of the proposed method in application to UHVDC systems. In addition, the analysis of voltage & current stresses of thyristors and the estimation of power losses have been carried out. Comparisons of the proposed method with that in [23] have been made.